The present invention pertains to integrated circuit (IC) memory devices, and, in particular, to an IC memory that combines both dynamic random access memory (DRAM) and electrically erasable programmable read only memory (EEPROM) on the same substrate for fast initial transfer of data to the DRAM and subsequent slower backup copy to the EEPROM.
In some applications it is desirable to use both volatile memory, such as DRAM, and non-volatile memory, such as EEPROM, in the same device. By way of example, it is desirable to have EEPROM to keep track of a cable television descrambler configuration and authorized premium channels, but it is too costly and too slow. Therefore, DRAM has been preferred as the storage medium of choice in the latter instance because of its considerably lower cost per bit, and the faster write time available to download data into memory, as compared to EEPROM.
One of the problems encountered in developing such a split memory for backup purposes pertains to the technique and timing of transfer of the contents from the initial memory to the backup memory. In the case of DRAM, memory locations must be refreshed periodically to avoid data loss that would otherwise occur as a consequence of cell leakage currents. Although the necessary refresh may be accomplished using the main processing unit of the system, (MPU, or processor), the desire to unburden the processor of refresh timing dictates the use of logic local to the DRAM for cycling and refreshing the memory locations independent of the processor.
The transparent refresh logic operates continuously in the refresh mode except when interrupted by the processor each time a memory location of the DRAM is accessed by the system. System access is constrained sufficiently to assure that all locations are refreshed within the retention time of the DRAM memory cells. Normally, the refresh logic cycles through all of the memory locations in ascending order of their addresses, and, as each location is addressed, all of the bits on that row are read out through sense amplifiers and then rewritten back into memory. This read out and write back operating mode is characteristic of all DRAM memory refresh systems.
In the case of an EEPROM, data is written into memory by application of high voltage signals to the cells to inject the appropriate charge into the storage medium, which may be either a floating poly-silicon gate or an oxy-nitride interface. Whichever of these storage media is utilized, the time required for the write cycle typically ranges from hundreds of microseconds to several milliseconds, and is considerably greater than the time typically allocated to the write cycle for a DRAM cell. It is customary to incorporate logic into the EEPROM IC (or chip) to self-time the write cycle and thereby relieve the processor from the burdens of controlling the timing and of the need to wait for completion of the write cycle.
The present invention is based in part on the recognition of the great similarity between the logic required to control the DRAM refresh system and the logic employed to control the EEPROM write cycles.
In normal operation, a computer system will update and modify the contents of any incorporated DRAM. Because of the volatility of this storage medium, the contents of the DRAM will be lost in the event of a power failure. To assure that the data is maintained, it may be transferred to an EEPROM so that the EEPROM always has available the latest copy of the DRAM memory contents. The availability of the data in this manner allows the system to be restored and the operation restarted on power up, as though no power failure had occurred.
The period of time required for transferring the data from the DRAM into the EEPROM is of no great concern in the system operation because the computer is not normally addressing the EEPROM directly. However, this period is of significance when a power failure occurs, because the transfer period must be of sufficient duration to ensure that in a worse case scenario the entire contents of the DRAM memory will be transferred. That is, if the transfer of data is interrupted by a power failure, adequate independent power supply must be available to keep the chip "alive" while the last remaining bytes are transferred to the EEPROM memory. The length of the period in question is readily determined from an analysis of the proposed system, the maximum rate of data change in the DRAM, and the duration of the EEPROM write cycle.
It is an object of the present invention to provide a memory chip that combines non-volatile and volatile storage media on the same substrate.
In particular, it is another object of the invention to provide a combined DRAM and EEPROM memory system which utilizes this similarity in control logic to link the DRAM refresh and EEPROM write cycle operations, and to facilitate the EEPROM backup of the DRAM.
Another object of the invention is to provide such a combined, mixed, or split memory chip for fast initial transfer of data to the lower cost, faster write time volatile storage medium, with transparent backup of selected contents of the latter medium in non-volatile storage.
It is, therefore, another object of the invention to provide a method and apparatus for a non-volatile memory backup of a volatile memory, in which the backup is performed in such a way that the normal functions and uses of the volatile memory in terms of reading and writing data under the control of the system processor are unaffected by the procedure for backing up the data, and the backup is substantially continuous to assure availability in the backup memory of the latest data stored in the volatile memory to preclude loss of data in a power failure independently of externally accessing the volatile memory to read data therefrom or write new data therein.
Still another object of the present invention is to provide such apparatus in which separate hardware for the logical compare function is fabricated in the same monolithic chip with one or both of the memories.